The present invention relates to a gate array for implementing a digital integrated circuit which is applicable to a variety of systems such as a computer system.
A gate array of the kind described has an input/output (I/O) buffer area in a peripheral region thereof and an internal logic area which is surrounded by the peripheral I/O area. While the I/O area has a comparatively high driving ability, the internal logic area has a comparatively low driving ability. Arranged regularly in the internal logic area are one or more cells of a single kind each comprising a plurality of transistors, resistors, and wiring regions. The elements in each cell are interconnected by wiring to constitute a desired logic circuit.
A prerequisite with the above-described prior art gate array is that the individual cells in the internal logic area and, therefore, the transistors built in each of the cells be miniature enough to satisfy the demand for minimal current consumption. The driving ability available with the prior art gate array is therefore limited. A substantial load cannot be applied to the circuit unless an extra number of circuit stages are included for scattering the load, resulting in an increase in delay time of the circuit.